1. Field of the Invention
The invention relates in general to a method of fabricating a flash memory, and more particularly, to a method of a flash memory in which an overlapping area between a floating gate and a control gate is increased.
2. Related Art of the Invention
Flash memory has been broadly applied in personal computer and electronic products due to the superior data retention characteristics.
The typical flash memory has a stack-gate structure, which comprises a tunneling oxide layer, a polysilicon floating gate used to store charges, a silicon oxide/silicon nitride/silicon oxide (ONO) dielectric layer, and a polysilicon control gate used to control the data access.
Normally, the larger the gate-coupling ratio (GCR) between the floating gate and the control gate, the lower the operation voltage required. Consequently, operation speed and efficiency are greatly enhanced. The method of increasing the gate-coupling ratio includes increasing the overlap area, the thickness of the dielectric layer, and the dielectric constant k of the dielectric layer between the floating gate and the control gate.
As mentioned above, increasing the overlap area between the floating gate and the control gate is advantageous to increasing the gate-coupling ratio. However, due to the continuous demand of higher integration, the area occupied by each memory cell has to be reduced. Therefore, how to fabricate a flash memory with a high gate-coupling rate within limited chip area has become an important task.